rom.vhd

基于ROM的正弦波发生器的设计:使用MATLAB得到这64个波形数据

library ieee;
use ieee.std_logic_1164.all;
entity rom is

port(
	clk: in std_logic;
	wave: out std_logic_vector(7 downto 0));
end rom;

library ieee;


library ieee;
use ieee.std_logic_1164.all;
entity counter is

port(clk: in std_logic;
	index: out integer range 0 to 63);
end counter;

architecture counter of counter is
begin
	
	process(clk)
	variable m:integer;
	begin
	if(clk'event and clk='1')then
	if(m = 63)then m:=0;
	else m:=m+1;
	end if;
	end if;
	index <= m;
	end process;
end counter;

library ieee;
use ieee.std_logic_1164.all;

entity lock is
port(
	clk:in std_logic;
	indata: in std_logic_vector(7 downto 0);
	outdata: out std_logic_vector(7 downto 0));
end lock;

architecture beha of lock is
begin
	process(clk)
	variable temp:std_logic_vector(7 downto 0);

	begin
	temp:=indata;
	if(clk'event and clk='1')then outdata<=temp;
	end if;
	end process;
end beha;


library ieee;
use ieee.std_logic_1164.all;

entity rom_1 is

port(addr: in integer range 0 to 63;
	data: out std_logic_vector(7 downto 0));
end rom_1;

architecture rom of rom_1 is
	type vector_array is array (0 to 63) of std_logic_vector(7 downto 0);
	constant memory:vector_array:=(
"10000000",
"10001100",
"10011000",
"10100101",
"10110000",
"10111100",
"11000110",
"11010000",
"11011010",
"11100010",
"11101010",
"11110000",
"11110101",
"11111010",
"11111101",
"11111110",
"11111111",
"11111110",
"11111101",
"11111010",
"11110101",
"11110000",
"11101010",
"11100010",
"11011010",
"11010000",
"11000110",
"10111100",
"10110000",
"10100101",
"10011000",
"10001100",
"10000000",
"01110011",
"01100111",
"01011010",
"01001111",
"01000011",
"00111001",
"00101111",
"00100101",
"00011101",
"00010101",
"00001111",
"00001010",
"00000101",
"00000010",
"00000001",
"00000000",
"00000001",
"00000010",
"00000101",
"00001010",
"00001111",
"00010101",
"00011101",
"00100101",
"00101111",
"00111001",
"01000011",
"01001111",
"01011010",
"01100111",
"01110011"
									);
begin
	data<=memory(addr);
	
end rom;


architecture structural of rom is

signal t1:integer range 0 to 63;
signal t2:std_logic_vector(7 downto 0);

component counter
port(clk: in std_logic;
	index:out integer range 0 to 63);
end component;

component rom_1
port(addr: in integer range 0 to 63;
	data: out std_logic_vector(7 downto 0));
end component;

component lock
port(
	clk:in std_logic;
	indata: in std_logic_vector(7 downto 0);
	outdata: out std_logic_vector(7 downto 0));
end component;

begin
u0: counter port map(clk,t1);
u1: rom_1 port map(t1,t2);
u2: lock port map(clk,t2,wave);
end structural;