xianshi.vhd

来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· VHDL 代码 · 共 54 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xianshi is
port(cle,clk1,clk9,clk10,clear,set:in std_logic;
                                 y:out std_logic_vector(6 downto 0);
                         jiedi,q0,q1:out std_logic);
end xianshi;

architecture one of xianshi is
component jishu2
port(clk,clr:in std_logic;
               q:out std_logic);
end component;

component yima2
port(m:in std_logic;
     q0,q1:out std_logic);
end component;

component jishu10
port(clk,clr,set:in std_logic;
               q:out std_logic_vector(3 downto 0));
end component;

component duolufuyong
port(sa,sb:in std_logic;
       a,b:in std_logic_vector(3 downto 0);
         q:out std_logic_vector(3 downto 0));
end component;

component qiduanyima
port(a,b,c,d:in std_logic;
            y:out std_logic_vector(6 downto 0));
end component;

signal jishu2q,yima2q0,yima2q1:std_logic;
signal jishu101q,jishu102q,duolufuyongq:std_logic_vector(3 downto 0);

begin
d1:jishu2       port map(clk1,cle,jishu2q);
s1:yima2        port map(jishu2q,yima2q0,yima2q1);
k1:jishu10      port map(clk9,clear,set,jishu101q);
k2:jishu10      port map(clk10,clear,set,jishu102q);
w1:duolufuyong  port map(yima2q0,yima2q1,jishu101q,jishu102q,duolufuyongq);
g1:qiduanyima   port map(duolufuyongq(0),duolufuyongq(1),duolufuyongq(2),duolufuyongq(3),y);
jiedi<='0';
q0<=yima2q0;
q1<=yima2q1;
end one;