代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/457446/7325464
vhi vgamem.vhi
-- VHDL Instantiation Created from source file vgamem.vhd -- 16:22:49 03/20/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std
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vhd giftest.vhd
-- VHDL Test Bench Created from source file gif.vhd -- 15:30:39 03/22/2004
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
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vhd lzw.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lzw is
Port ( start,resetin, clk : in std_logic;
addr : out std_
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vhd xianshi.vhd
--利用列扫描信号显示数码管
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
port(
clk : in std_logic;
sel : in std_logic_vector(2 downto 0);
ledms1: out
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vhd delay.vhd
-- 延迟，起时钟同步作用。因为HELLO模块有时钟同步，所以送出的列值比送到
--端口上的列选择信号玩一个时钟周期。此模块延时使HELLO模块与tingche模块同步。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay is
port(
clk:
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vhd gewei.vhd
--数码管显示提车位个数个位
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity gewei is
port(
clk : in std_logic;
chewei : in std_logi
www.eeworm.com/read/457284/7328729
vhd sel.vhd
-----------------------------------------------------------------------
--该模块实现在停车场有汽车时，对８×８点阵的列选信号的确定
--本设计中列选信号是每过一个时钟周期就变化一次的
--通过这种快速的扫描实时输出停车场状态信息(即有没有有汽车进出)
---------------------------------
www.eeworm.com/read/457284/7328731
vhd fenpin.vhd
--为了显示效果更佳，将时钟适当分频；此模块可不用
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fenpin is
port(
clk:in std_logic;
fenpin:out s
www.eeworm.com/read/457284/7328831
vhd shiwei.vhd
--数码管显示停车位个数的十位
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity shiwei is
port(
clk : in std_logic;
chewei : in std_
www.eeworm.com/read/456678/7342403
vhd dds.vhd
--DDS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT(K : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CL