代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/459164/7279416
vhd receiver.vhd
--异步接收电路VHDL程序。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity receiver is
port (rst,clk,rxd,ERBF : in std_logic ;
dout : out std_logic_vector (7 downto 0) ;
www.eeworm.com/read/458097/7313244
vhd lab9bench.vhd
---------------------------------------------------------------------------------
---- Digital Systems Design - VHDL and Programmable Logic Devices
---- Instructor: Dr. C. S. Lin
---- T.A.: Fadi
www.eeworm.com/read/458097/7313252
bak lab9bench.vhd.bak
---------------------------------------------------------------------------------
---- Digital Systems Design - VHDL and Programmable Logic Devices
---- Instructor: Dr. C. S. Lin
---- T.A.: Fadi
www.eeworm.com/read/457723/7318712
vhd extcomp.vhd
--*******************************************************************--
-- Copyright (c) 1999-2000 Evatronix Ltd. --
--****************************************************
www.eeworm.com/read/457722/7318747
vhd portx.vhd
--**********************************************************************************************
-- Parallel Port Peripheral for the AVR Core
-- Version 0.3 02.11.2002
-- Designed by Ruslan Lep
www.eeworm.com/read/457464/7325262
vhd system.vhd
-- ------------------------------------------------
-- Model : Top - Level System Component
--
-- Author : Michael Mayer,
-- Department of Electrical Engineering
--
www.eeworm.com/read/457450/7325367
vhd vga.vhd
-------------------------------------------------------------------------------
-- vga.vhd
--
-- Author(s): Ashley Partis and Jorgen Peddersen
-- Created: Jan 2001
-- Last Modified: Jan
www.eeworm.com/read/457446/7325394
vhi headers.vhi
-- VHDL Instantiation Created from source file headers.vhd -- 16:19:09 03/20/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and st
www.eeworm.com/read/457446/7325425
vhd register2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register2 is
Port (clk, reset: in std_logic;
cop: in std_logic_vector
www.eeworm.com/read/457446/7325439
vhd mux6.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux6 is
Generic ( size : integer := 8 );
Port ( d0 : in std_logic_vector(