代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/462742/7196629
vhd reg1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg1 is
port(d: in std_logic_vector(31 downto 0);
clk:in std_logic;
q:out std_logic_vector(31 downto 0));
end entity reg1;
a
www.eeworm.com/read/462742/7196630
vhd adder32.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32 is
port(n: in std_logic_vector(31 downto 0);
a: in std_logic_vector(31 downto 0);
cl
www.eeworm.com/read/462742/7196631
vhd reg2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg2 is
port(e: in std_logic_vector(31 downto 0);
clk:in std_logic;
p:out std_logic_vector(31 downto 0));
end entity reg2;
a
www.eeworm.com/read/462646/7198871
vhd contador.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Jose Abraham Caravaca Fernandez
--
-- Create Date: 10:51:24 11/27/08
-- Design Name:
www.eeworm.com/read/462290/7203379
vhd count10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count10 is
port(reset : in std_logic;
enable : in std_logic;
clk : in
www.eeworm.com/read/462120/7209143
vhd mux21w16.vhd
-- output of CoreGen module generator
-- $Header: mux2VHT.vhd,v 1.2 1998/06/15 17:57:53 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/462120/7209153
vhd mux4w16.vhd
-- output of CoreGen module generator
-- $Header: mux4VHT.vhd,v 1.2 1998/06/15 17:58:03 tonyw Exp $
-- ************************************************************************
-- Copyright 1996-19
www.eeworm.com/read/462030/7212075
vhd alu8.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/461652/7222750
vhd serial.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/461652/7222762
vhd interface.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia