contador.vhd

来自「This sources implement a 8-bit FIR Filte」· VHDL 代码 · 共 65 行

--------------------------------------------------------------------------------
-- Company: 
-- Engineer: Jose Abraham Caravaca Fernandez
--
-- Create Date:    10:51:24 11/27/08
-- Design Name:    Contador para Filtro
-- Module Name:    Contador - Behavioral
-- Project Name:   MAC_FIR
-- Target Device:  XC3s400
-- Tool versions:  
-- Description:	 Counts from 0 to 7
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Contador is
	 Generic ( n : positive := 3);
    
	 Port ( reset : in std_logic;
           ce : in std_logic;
           ir : in std_logic;
           load : in std_logic;
           din : in std_logic_vector(n-1 downto 0);
           clk : in std_logic;
           fcount : out std_logic;
			  count : out std_logic_vector(n-1 downto 0));
end Contador;

architecture Behavioral of Contador is

signal count_aux: unsigned (n-1 downto 0);
signal top_aux: unsigned (n-1 downto 0):=(others => '1');

begin
	if reset='1' then
		count_aux <= (others => '0');
	
	else if clk='1' and clk'EVENT THEN
		if load='1' then
			count_aux <= unsigned(din);
		
		else
			if ce='1' then
				if dir='1' then
					count_aux <= count_aux + 1;
					if count_aux = top_aux then
						fcount <= '1';
					end if
				else
					count_aux <= count_aux - 1;
				end if;
			end if;
		end if;
	end if;
end process;

count <= std_logic_vector(count_aux);

end Behavioral;