reg2.vhd

来自「利用EDA硬件描述语言来实现DDS功能」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
entity reg2 is
   port(e: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        p:out std_logic_vector(31 downto 0));
end entity reg2;
architecture art  of reg2 is
  begin
process(clk) is
  begin 
if clk'event and clk='1'then
   p<=e;
end if;
end process;
end architecture art;