count10.vhd

vhdl实现的计数器,可以从0记到999,该代码使用模块化设计思想,开发工具muxplus2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count10 is
		port(reset : in std_logic;
			 enable : in std_logic;
			 clk : in std_logic;
			 cout : out std_logic;
			 q : out std_logic_vector(3 downto 0));
end count10;
architecture rtl of count10 is
	signal q_temp: std_logic_vector(3 downto 0);
begin 
	process(clk)
	begin
		if(clk'event and clk='1')then
			if(reset='1')then
				q_temp<=(others=>'0');
			elsif(enable='1')then
				if(q_temp="1001")then
					q_temp<=(others=>'0');
				else q_temp<=q_temp+1;
			end if;
		end if;
		end if;
		q<=q_temp;
	end process;
	cout<='1' when q_temp="1001"and enable='1'
			else '0';
end rtl;