reg1.vhd

来自「利用EDA硬件描述语言来实现DDS功能」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
entity reg1 is
   port(d: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        q:out std_logic_vector(31 downto 0));
end entity reg1;
architecture art  of reg1 is
  begin
process(clk) is
  begin 
if clk'event and clk='1'then
   q<=d;
end if;
end process;
end architecture art;