adder32.vhd

来自「利用EDA硬件描述语言来实现DDS功能」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32 is
   port(n: in std_logic_vector(31 downto 0);
        a: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        en:in std_logic;
        out2:out std_logic_vector(31 downto 0));
end entity adder32;
architecture art of adder32 is
  signal b:std_logic_vector(31 downto 0);
begin
process(clk,en) is
  begin 
if clk'event and clk='1'then
   if en='1'then
      b<=a+n;
    end if;
   end if;
    out2<=b;
end process;
end architecture art;