代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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vhd reg1.vhd

--REG1.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG1 IS PORT(D: IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLK: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END ENTITY
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vhd reg2.vhd

--REG2.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG2 IS PORT(D: IN STD_LOGIC_VECTOR(8 DOWNTO 0); CLK: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END ENTITY
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vhd genxlib_arch.vhd

-------------------------------------------------------------------------------- -- Copyright(C) 2005 by Xilinx, Inc. All rights reserved. -- This text/file contains proprietary, confidential -- in
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vhd reject.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity reject1 is Port (clk : in std_logic; mode : in std_logic;
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vhd demo_all.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demo_all is Port (clk : in std_logic; mode : in std_logic_vector(5
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vhd mode_cymometer.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03:33:14 03/25/05 -- Design Name: -- Module Name: mode_cym
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www.eeworm.com/read/464190/7167791

vhd lcd.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lcd_6 is Port ( clk,rst,ce : in STD_LOGIC; sf_ce0 : out STD
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www.eeworm.com/read/464013/7170834

vhd clk.vhd

library ieee; use ieee.std_logic_1164.all; entity clk is port(clkin:in std_logic; seg1:out std_logic_vector(3 downto 0); seg2:out std_logic_vector(3 downto 0); seg3:out std_logic_vector(3 d
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www.eeworm.com/read/464013/7170925

vhd fen60.vhd

------------------------------------------------- --实体名：fen60 --功 能：60进制计数器 --接 口：clk -时钟输入 -- qout1-个位BCD输出 -- qout2-十位BCD输出 -- carry-进位信号输出 --作 者：Haibing Li --日 期：
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www.eeworm.com/read/463790/7175126

vhd qwe1.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder38 is port (Q0: out std_logic_vector(7 downto 0); Q1: in std_logic_vector(2 downto 0); g1,g2,g3:
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