mode_cymometer.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    03:33:14 03/25/05
-- Design Name:    
-- Module Name:    mode_cymometer - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mode_cymometer is
    Port ( ireset : in std_logic;
           clka : in std_logic;
           clkb : in std_logic;
           tclk : in std_logic;
           dout : out std_logic_vector(23 downto 0));
end mode_cymometer;

architecture Behavioral of mode_cymometer is

type state is (st0,st1,st2,st3,st4,st5,st6);
signal current_state : state;

signal kd : std_logic;  --1秒钟的闸门信号；
begin
process(clkb)
begin
   if rising_edge(clkb) then 
      kd<=not(kd);
   end if;
end process;

process(clka,ireset)
variable ris_a,ris_b : std_logic;
variable cnt1 : std_logic_vector(3 downto 0);
variable cnt2 : std_logic_vector(3 downto 0);
variable cnt3 : std_logic_vector(3 downto 0);
variable cnt4 : std_logic_vector(3 downto 0);
variable cnt5 : std_logic_vector(3 downto 0);
variable cnt6 : std_logic_vector(3 downto 0);
begin
   if ireset='1' then ris_b:='0';ris_a:='0';
         cnt6:="0000";cnt5:="0000";cnt4:="0000";
	    cnt3:="0000";cnt2:="0000";cnt1:="0000";
   elsif rising_edge(clka) then
      if kd='1' then ris_b:='0';
	    if tclk='1'and ris_a='0' then ris_a:='1';
         elsif tclk='0'and ris_a='1' then ris_a:='0';
	       if cnt1="1001" then cnt1:="0000";
	         if cnt2="1001" then cnt2:="0000";
		      if cnt3="1001" then cnt3:="0000";
			    if cnt4="1001" then cnt4:="0000";
			       if cnt5="1001" then cnt5:="0000";
				     if cnt6="1001" then cnt6:="0000";
				     else cnt6:=cnt6+1; end if;
			       else cnt5:=cnt5+1; end if;
			    else cnt4:=cnt4+1; end if;
		      else cnt3:=cnt3+1;end if; 
	        else cnt2:=cnt2+1; end if;
	      else cnt1:=cnt1+1; end if;
         end if;
      elsif ris_b='0' then ris_b:='1';
	    dout<=cnt6&cnt5&cnt4&cnt3&cnt2&cnt1;
      else 
	    cnt6:="0000";cnt5:="0000";cnt4:="0000";
	    cnt3:="0000";cnt2:="0000";cnt1:="0000";
	 end if;
   end if;
end process;
end Behavioral;