reject.vhd

总体演示程序DEMO_FPGA.rar

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reject1 is
    Port (clk : in std_logic;
	       mode : in std_logic;
	       ibutton : in std_logic;
			 ibut,ibut1 : in std_logic;
	       cs,cs1 : out std_logic;
	       pout : out std_logic_vector(7 downto 0) );
end reject1;

architecture Behavioral of reject1 is
signal div_mode : std_logic_vector(3 downto 0);
signal clk10,button,but,but1 : std_logic;
signal clk100 : std_logic;
signal pout1 : std_logic_vector(7 downto 0);
signal del : integer range 0 to 500000;
begin	

process(ibut1,clk10)
variable t : std_logic_vector(1 downto 0);
begin
   if ibut1='1' then t:="00";
	elsif rising_edge(clk10) then
	   if t<"11" then t:=t+1;
		end if;
	end if;
	but1<=t(1);
end process;

process(ibut,clk10)
variable t : std_logic_vector(1 downto 0);
begin
   if ibut='1' then t:="00";
	elsif rising_edge(clk10) then
	   if t<"11" then t:=t+1;
		end if;
	end if;
	but<=t(1);
end process;

process(clk10)
begin
   if rising_edge(clk10) then 
	   if but='1' then  
 	      if del>50000 then del<=del-50000;
		   else del<=50000;
		   end if;
		elsif but1='1' then 
	      if del<400000 then del<=del+50000;
		   else del<=450000;
	      end if;
		end if;
	end if;
end process;
	 	
process(clk)
variable cnt : integer range 0 to 500000;
begin
   if rising_edge(clk) then cnt:=cnt+1;
	   if cnt<del then 	clk100<='1';
		elsif cnt<500000 then clk100<='0';
		else cnt:=0;
		end if;
   end if;
end process;

process(clk)
variable cnt : integer range  0 to 5000000;
begin
   if rising_edge(clk) then cnt:=cnt+1;
	   if cnt<5000000 then 	clk10<='0';
		elsif cnt<10000000 then clk10<='1';
		else cnt:=0;
		end if;
   end if;
end process;

process(ibutton,clk10)
variable t : std_logic_vector(2 downto 0);
begin
   if ibutton='1' then t:="000";
	elsif rising_edge(clk10) then
	   if t<"11" then t:=t+1;
		end if;
	end if;
	button<=(t(1)xor t(0));
end process;
    
process(button,clk10)
variable cnt : integer range 0 to 6;
variable q1,q : std_logic_vector(7 downto 0);
begin
   if rising_edge(button) then
	  if cnt<3 then cnt:=cnt+1;
	  else cnt:=0;
	  end if;

	  if cnt=0 then q1:="11111110";
	  elsif cnt=1 then q1:="11111010";
	  elsif cnt=2 then q1:="11101010";
	  else q1:="10101010";
	  end if;
   end if;

	if button='1' then q:=q1;
	elsif rising_edge(clk10) then
	   q:=q(6 downto 0)&q(7);
		pout1<=q;
	end if;
end process;

process(mode)
begin
   if mode='0' then cs<='1';cs1<='0';
	   if clk100='1' then pout<=pout1;
		else pout<="11111111";
		end if;
	else cs1<='1';pout<="11111111";
	end if;
end process;
end Behavioral;