qwe1.vhd

来自「3-8译码器和8-3BCD七段显示译码器」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder38 is 
port (Q0: out std_logic_vector(7 downto 0);
   Q1: in std_logic_vector(2 downto 0);
   g1,g2,g3: in std_logic);
end entity decoder38;
architecture code1 of decoder38 is
 begin
 process(Q1,g1,g2,g3)
 variable temp : std_logic_vector(7 downto 0);
 begin
  if (g1 = '0' or g2='1' or g3='1' )then temp := "ZZZZZZZZ";
   else
    case Q1 is
     when "000" => temp := "11111110";
     when "001" => temp := "11111101";
     when "010" => temp := "11111011";
     when "011" => temp := "11110111";
     when "100" => temp := "11101111";
     when "101" => temp := "11011111";
     when "110" => temp := "10111111";
     when "111" => temp := "01111111";
    end case;
end if;
  Q0 <= temp;
 end process;
end architecture code1;