demo_all.vhd

总体演示程序DEMO_FPGA.rar

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demo_all is
    Port (clk : in std_logic;
	       mode : in std_logic_vector(5 downto 0);
			 button : in std_logic_vector(7 downto 0);
			 cs : out std_logic_vector(1 downto 0);
			 led : out std_logic_vector(7 downto 0);
			 led_shift : out std_logic_vector(3 downto 0);
			 tone : out std_logic;
			 itclk : in std_logic;
			 otclk : out std_logic;
			 ichose : in std_logic;
		 -----------------------
           lcdda : out std_logic;
           lcdrw : out std_logic;
           lcden : out std_logic;
           dout_lcd  : out std_logic_vector(7 downto 0);
		 ----------------------------
		 din_adc : in std_logic;
		 clk_tlc549 : out std_logic;
           cs_tlc549  : out std_logic);
end demo_all;

architecture Behavioral of demo_all is
component demo1 
    Port (clk : in std_logic;
	       a,b,c,d,e,f,g,h : in std_logic;
			 tone : out std_logic);
end component;

component Songer                                      -- 顶层设计
    PORT (    clk    : in  std_logic; 
             --  CODE1  : OUT std_logic_vector(2 downto 0);
             --  HIGH1  : OUT STD_LOGIC; 
             SPKOUT   : OUT STD_LOGIC );
end component;

component demo2 
    Port (clk : in std_logic;
	       imode : in std_logic_vector(2 downto 0);
	       ibutton : in std_logic;
			 cs,cs1 : out std_logic;
			 led : out std_logic_vector(7 downto 0);
			 led_shift : out std_logic_vector(3 downto 0));
end component;

component reject1 
    Port (clk : in std_logic;
	       mode : in std_logic;
	       ibutton : in std_logic;
			 ibut,ibut1 : in std_logic;
	       cs,cs1 : out std_logic;
	       pout : out std_logic_vector(7 downto 0) );
end component;

component Top_FPGA_demo
     Port (clk : in std_logic;						--50m系统时钟
           -------------------------
           ienter : in std_logic;
           istepa : in std_logic;
           istepb : in std_logic;
           ichose : in std_logic;
           ireset : in std_logic;
		 -------------------------
		 button : in std_logic_vector(3 downto 0);
		 --------------------------
		 tone : out std_logic;
		 -----------------------
		 itclk : in std_logic;
		 otclk : out std_logic;
		 -----------------------
           lcdda : out std_logic;
           lcdrw : out std_logic;
           lcden : out std_logic;
           dout_lcd  : out std_logic_vector(7 downto 0);
		 ----------------------------
		 din_adc : in std_logic;
		 clk_tlc549 : out std_logic;
           cs_tlc549  : out std_logic;	
		 shift      : out std_logic_vector(3 downto 0);			
		 cs_led     : out std_logic_vector(1 downto 0);
		 dout_led   : out std_logic_vector(7 downto 0));
end component;

signal ienter,istepa,istepb,ireset : std_logic;
signal button3a : std_logic_vector(3 downto 0);
signal shift3 : std_logic_vector(3 downto 0);
signal cs3 : std_logic_vector(1 downto 0);
signal dout3 : std_logic_vector(7 downto 0);
signal tone3 : std_logic;


signal clk1,clk2,clk3,clk4 : std_logic;
signal button1 : std_Logic_vector(7 downto 0);
signal tone1 : std_logic;
signal tone2 : std_Logic;
signal mode1 : std_logic_Vector(2 downto 0);
signal mode2 : std_logic;
signal button2,button3,but,but1 : std_logic;
signal css,csss : std_logic_vector(1 downto 0);
signal led1,led2 :std_logic_vector(7 downto 0);
signal led1_sh : std_logic_vector(3 downto 0); 
begin
   u0: demo1 port map(clk=>clk,a=>button1(7),b=>button1(6),c=>button1(5),d=>button1(4),e=>button1(3),f=>button1(2),g=>button1(1),h=>button1(0),tone=>tone1);
   u1: songer port map(clk=>clk,spkout=>tone2);
   u2: demo2 port map(clk=>clk,imode=>mode1,ibutton=>button2,cs=>css(1),cs1=>css(0),led=>led1,led_shift=>led1_sh);
   u3: reject1 port map(clk=>clk,mode=>mode2,ibutton=>button3,ibut=>but,ibut1=>but1,cs=>csss(1),cs1=>csss(0),pout=>led2);
   u4: Top_FPGA_demo port map(clk=>clk,ienter=>ienter,istepa=>istepa,istepb=>istepb,
                              ichose=>ichose,ireset=>ireset,button=>button3a,
						tone=>tone3,itclk=>itclk,otclk=>otclk,
						lcdda=>lcdda,lcdrw=>lcdrw,lcden=>lcden,
						dout_lcd=>dout_lcd,din_adc=>din_adc,
						clk_tlc549=>clk_tlc549,cs_tlc549=>cs_tlc549,
						shift=>shift3,cs_led=>cs3,dout_led=>dout3);


process(mode)
begin
   case mode is
     when "111111"=>
	              	      cs<=cs3;led<=dout3;ireset<=button(0);ienter<=button(3);istepa<=button(1);istepb<=button(2);
					 button3a<=button(7 downto 4);tone<=tone3;
	when "011111"=>																				 --发光二极管；
	              mode2<='0';cs<="01";button3<=button(0);led<=led2;but<=button(2);but1<=button(3);
   when "011110"=>
					  mode2<='0';cs<="01";button3<=button(0);led<=led2;but<=button(2);but1<=button(3);
					  tone<=tone2;
   when "101111"=>
	              mode1<="011";button2<=button(1);cs<="10";led<=led1;led_shift<=led1_sh;
	when "101110"=> 
					  mode1<="011";button2<=button(1);cs<="10";led<=led1;led_shift<=led1_sh;
					  tone<=tone2;
	when "110111"=>
	 				  mode1<="101";button2<=button(1);cs<="10";led<=led1;led_shift<=led1_sh;
	when "110110"=>
					  mode1<="101";button2<=button(1);cs<="10";led<=led1;led_shift<=led1_sh;
					  tone<=tone2;
	when "111011"=>
	 				  mode1<="110";button2<=button(1);cs<="10";led<=led1;led_shift<=led1_sh;
	when "111110"=>
					  mode1<="110";button2<=button(1);cs<="10";led<=led1;led_shift<=led1_sh;
					  tone<=tone2;cs<="11";led<="11111111";
   when "111101"=>
	              button1<=button;tone<=tone1;
   when others=>
	              cs<="11";led<="11111111";
   end case;
end process;
end Behavioral;