clk.vhd

来自「一个时钟计数器」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;

entity clk is
port(clkin:in std_logic;
	seg1:out std_logic_vector(3 downto 0);
	seg2:out std_logic_vector(3 downto 0);
	seg3:out std_logic_vector(3 downto 0);
	seg4:out std_logic_vector(3 downto 0);

	seg5:out std_logic_vector(3 downto 0);
	seg6:out std_logic_vector(3 downto 0));
end entity;

architecture one of clk is
component second is
port
(clk:in std_logic; qout:out std_logic);
end component;
component fen24 is 
port
(clk   : in  std_logic;
 qout1 : out std_logic_vector(3 downto 0);
 qout2 : out std_logic_vector(3 downto 0));
end component;
component fen60 is 
port
(clk   : in  std_logic;
 qout1 : out std_logic_vector(3 downto 0);
 qout2 : out std_logic_vector(3 downto 0);
 carry : out std_logic);
end component;
signal a,b,c:std_logic;
begin
--u1:second port map(clk=>clkin,qout=>a);
u2:fen60 port map(clk=>clkin,carry=>b,qout1=>seg1,qout2=>seg2);
u3:fen60 port map(clk=>b,carry=>c,qout1=>seg3,qout2=>seg4);
u4:fen24 port map(clk=>c,qout1=>seg5,qout2=>seg6);
end architecture one;