代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/341927/7103553
vhd time.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time is
port(clk:in std_logic; --时钟500Hz
reset:in std_logic; --复位信号
start:in std_logic;
www.eeworm.com/read/398287/7105068
vhd sram.vhd
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--*************************************************************************************************
www.eeworm.com/read/398287/7105079
vhd frequency.vhd
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--*************************************************************************************************
www.eeworm.com/read/398287/7105089
vhd flash.vhd
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--*************************************************************************************************
www.eeworm.com/read/138637/7107852
vhd i2cbasics_package.vhd
--------------------------------------------------------------------------------
-- i2cBasics (Package for i2c basic modules)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c / 20, Jun., 2005
--
------
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vhd t_regi2csm.vhd
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-- Test module for regI2cSlave and regI2cMaster
-- T.Kohno
-- Rev. 0.1.1c / 16, Jun., 2005
------------------------
www.eeworm.com/read/138637/7107856
vhd~ t_regi2csm.vhd~
--------------------------------------------------------------------------------
-- Test module for regI2cSlave and regI2cMaster
-- T.Kohno
-- Rev. 0.1.1 / 16, Jun., 2005
-------------------------
www.eeworm.com/read/138637/7107862
vhd dac7615c.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DAC7615C is
Port ( ADC1 : in std_logic_vector(11 downto 0); --Channel1 input
www.eeworm.com/read/138637/7107864
vhd dac902c.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dac902c is
Port ( clk : in std_logic;
reset : in std_logic;
www.eeworm.com/read/329914/7109680
bak clock_pkg.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package clock_pkg is
component hour is
port( hh,hl : buffer std_logic_vector (3 downto