代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/468784/6988445
vhd ym2149_volmix.vhd
--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or w
www.eeworm.com/read/326018/6991023
txt tushuguan.txt
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hehe1 is
port(
rst:in std_logic; --复位
clk: in std_logic;
rxd: in s
www.eeworm.com/read/468520/6992161
vhd unishift74194.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift74194 is
port(clk, cr, rin,lin: in std_logic;
s: in std_logic_vector
www.eeworm.com/read/468520/6992172
bak shiftreg7495.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift7495 is
port(clk, cr, rin,lin: in std_logic;
s: in std_logic_vector(
www.eeworm.com/read/468520/6992174
vhd dec7418.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dec74138 is
port(g1,g2,g3: in std_logic;
a: in std_logic_vector(2 downto 0);
y: out
www.eeworm.com/read/468520/6992209
vhd mux74151.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux74151 is
port(en: in std_logic;
a: in std_logic_vector(2 downto 0);
d: in std_lo
www.eeworm.com/read/468520/6992220
bak mux74151.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux74151 is
port(en: in std_logic;
a: in std_logic_vector(2 downto 0);
d: in std_lo
www.eeworm.com/read/468520/6992221
vhd shiftreg7495.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift7495 is
port(clk, cr, rin,lin: in std_logic;
s: in std_logic_vector(
www.eeworm.com/read/468520/6992240
bak unishift74194.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift74194 is
port(clk, cr, rin,lin: in std_logic;
s: in std_logic_vector
www.eeworm.com/read/468520/6992247
bak dec7418.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dec74138 is
port(g1,g2,g3: in std_logic;
a: in std_logic_vector(2 downto 0);
y: out