mux74151.vhd

vhdl programs to use as a lab experiment all advance programs

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux74151 is
port(en: in std_logic;
		a: in std_logic_vector(2 downto 0);
		d: in std_logic_vector(7 downto 0);
		y: out std_logic
		);
end mux74151;
architecture reg of mux74151 is
signal sy: std_logic;
begin
	process(en, a,d)
	begin
		if en='1' then
		case a is
			when "000" => sy<= d(0);
			when "001" => sy<= d(1);
			when "010" => sy<= d(2);
			when "011" => sy<= d(3);
			when "100" => sy<= d(4);
			when "101" => sy<= d(5);
			when "110" => sy<= d(6);
			when "111" => sy<= d(7);
			when others => sy<= 'U';
		end case;
		end if;
	end process;
	y<= sy;
end reg;