tushuguan.txt

--功能描述 --1 刷卡后产生与本人身份唯一对应的串行二进制码元序列

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity hehe1 is
port(
    rst:in std_logic;   --复位
    clk: in std_logic;
	rxd: in std_logic;   --串行二进制码元
	wel:out std_logic;   --欢迎字样
	result:out std_logic  --匹配状态，即栅栏门开合
	);
end hehe1;


architecture behav of hehe1 is

    constant s0 :std_logic_vector(2 downto 0):="000";--等待并初始化
    constant s1 :std_logic_vector(2 downto 0):="001";--读入数据，串并转换
    constant s2 :std_logic_vector(2 downto 0):="011";--数据比较
    constant s3 :std_logic_vector(2 downto 0):="111";--匹配
    constant s4 :std_logic_vector(2 downto 0):="110";--缓冲，处理ROM延时
    constant s5 :std_logic_vector(2 downto 0):="100";--判断匹配，用于最后一位
    constant s6 :std_logic_vector(2 downto 0):="101";--缓冲，处理ROM延时
    shared variable count:integer range 0 to 9; 输入码元计数，初始值为8
    signal ss:std_logic_vector(2 downto 0);--状态
    signal address1: STD_LOGIC_VECTOR (4 DOWNTO 0); -ROM读取地址，初始值为0
    signal wrmemdata :std_logic_vector(7 downto 0); --并行二进制数
    signal redmemdata :std_logic_vector(7 downto 0); --ROM读取值

component store
	PORT
	(       address		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

begin
n1:store port map(address1,clk,redmemdata);
process(clk,rst,rxd)
  begin

    if rst='0' then
       ss<=s0;
    elsif clk'event and clk='1' then
       case ss is
      
         when s0=>
              result<='0';
              wel<='0';
              count:=9;
              address1(0)<='0';
              address1(1)<='0';
              address1(2)<='0';
              address1(3)<='0';
              address1(4)<='0';--内存地址初始化
           if rxd/='0' then
              ss<=s1;
            end if;

         when s1=>   --串并转换
                wrmemdata(7) <= wrmemdata(6);
		    	wrmemdata(6) <= wrmemdata(5);
				wrmemdata(5) <= wrmemdata(4);
				wrmemdata(4) <= wrmemdata(3);
				wrmemdata(3) <= wrmemdata(2);
				wrmemdata(2) <= wrmemdata(1);
				wrmemdata(1) <= wrmemdata(0);
				wrmemdata(0) <= rxd;          --串并转换
				count:=count-1;               --输入记数
            if count=0 then
              ss<=s2;         
            end if;

        when s2=>
            if wrmemdata=redmemdata then
               result <= '1';
               ss<=s3;
            else
              if address1=29 then
              ss<=s4;
             else 
               if address1=30 then
                ss<=s4;
               else 
               if address1=31 then 
                 ss<=s6;
               else address1<=address1+1;  --比较下一位
               end if;
              end if;
             end if;
            end if;

         when s3=>
             wel<='1';--如果匹配则欢迎
             ss<=s0; --继续下一个

         when s4=>
             ss<=s2;
             address1<=address1+1;
 
         when s5=>
             if wrmemdata=redmemdata then
               result <= '1';
               ss<=s3;
             else
               result<= '0';
               ss<=s0;
             end if;

          when s6=>
             ss<=s5;

          when others=>
           ss<=s0;
        end case;
     end if;
   end process;

end behav;