dec7418.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dec74138 is
port(g1,g2,g3: in std_logic;
		a: in std_logic_vector(2 downto 0);
		y: out std_logic_vector(7 downto 0)
		);
end dec74138;
architecture reg of dec74138 is
signal ys: std_logic_vector(7 downto 0);
begin
    process (g1,g2,g3, a)
        begin
        if (g1='1' and g2='1' and g3='1')then
        case a is
            when"000" => ys<="00000001";
		      when"001" => ys<="00000010";   
		      when"010" => ys<="00000100";
		      when"011" => ys<="00001000";
		      when"100" => ys<="00010000";
		      when"101" => ys<="00100000";
		      when"110" => ys<="01000000";
		      when"111" => ys<="10000000";
		      when others => ys<="UUUUUUUU";
		   end case;
		   end if;
	  end process;
	  y<= ys;
end reg;