shiftreg7495.vhd.bak

vhdl programs to use as a lab experiment all advance programs

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift7495 is
    port(clk, cr, rin,lin: in std_logic;
          s: in std_logic_vector(1 downto 0);
          d: in std_logic_vector(3 downto 0);
          q: out std_logic_vector(3 downto 0)
          );
end shift7495;
architecture reg of shift7495 is
signal sq: std_logic_vector(3 downto 0);
begin
    process(clk,cr,d)
        begin
            if(cr='1') then sq<= "0000";
            elsif(clk'event and clk='1') then
                case  s is
                 when "00" => sq<=d;
                 when "01" => sq<= rin& d(3 downto 1);
                 when "10" => sq<= d(2 downto 0)&lin;
                 when "11" => sq<= d(0)& d( 3 downto 1);
                 when others => sq<= "UUUU"; 
                end case ;
            end if; 
    end process; 
end reg;