代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/161896/10358347
vhd cmbwordtrig.vhd
library ieee;
use ieee.std_logic_1164.all;
entity cmbwordtrig is
port( data : in std_logic_vector(31 downto 0);
tword : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(
www.eeworm.com/read/161894/10358357
vhd debounce.vhd
--下层模块，防抖电路
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity debounce is
port(
key,cp:in std_logic;
imp:out std_logic);
en
www.eeworm.com/read/161894/10358360
vhd frelatch.vhd
--锁存器模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity frelatch is
port(
reset:in std_logic;
cp3:in std_logic;
overflow:in std_logic;
low:in std_log
www.eeworm.com/read/161894/10358369
vhd plj.vhd
--上层模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity plj is
port(
cp_20m:in std_logic;--20MHz时钟信号
enable:in std_logic;--开关信号
input:in std_logic;--输入被测
www.eeworm.com/read/161863/10359552
vhd bahe.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bahe is
port(clk_4m,man_left,man_right,clr1,judger: in std_logic;
judger_out:ou
www.eeworm.com/read/161863/10359566
vhd counter.vhd
--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*****************************
www.eeworm.com/read/161862/10359871
vhd yimaqi.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity yimaqi is
port(F1,F2:in std_logic;
Y3,Y2,Y1,Y0:out std_logic
);
end yimaqi ;
architecture behv of y
www.eeworm.com/read/353880/10408666
vhd serial.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/353880/10408718
vhd interface.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/353880/10408763
vhd mux.vhd
-------------------------------------------------------------------------------
-- Title : mux
-- Project :
-------------------------------------------------------------------------------
--