plj.vhd

四位十进制数码显示、量程自动转换的数字频率计。

--上层模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity plj is
	port(
		cp_20m:in std_logic;--20MHz时钟信号
		enable:in std_logic;--开关信号
		input:in std_logic;--输入被测信号
		reset:in std_logic;--复位信号
		sel:out std_logic_vector(3 downto 0);--输出片选信号
		show_1:out std_logic_vector(6 downto 0);--输出7位数码管显示
		show_2:out std_logic_vector(6 downto 0);
		show_3:out std_logic_vector(6 downto 0);
		show_4:out std_logic_vector(6 downto 0);
		decimal:out std_logic_vector(2 downto 0)--输出小数点
		);	
end plj;
architecture content of plj is
	signal cp_1,cp_2,cp_3:std_logic;
	signal reset_1:std_logic;
	signal overflow_1,low_1:std_logic;
	signal play0_1,play1_1,play2_1,play3_1:integer range 0 to 9;
	signal overlatch_1,lowlatch_1:std_logic;
	signal p0latch_1,p1latch_1,p2latch_1,p3latch_1:integer range 0 to 9;
	signal decimal_1:std_logic_vector(2 downto 0);
component dividefre4 is
	port(
		cp_20m:in std_logic;
		cp1:out std_logic;
		cp2:out std_logic;
		cp3:out std_logic
		);
end component;
component debounce is
	port(
		key:in std_logic;
		cp:in std_logic;
		imp:out std_logic
	);
end component;
component fretest is
	port(
		enable,cp3,input,reset:in std_logic;
		overflow,low:out std_logic;
		play0,play1,play2,play3:out integer range 0 to 9;
		decimal:out std_logic_vector(2 downto 0)
		);
end component;
component frelatch is
	port(
		reset:in std_logic;
		cp3:in std_logic;
		overflow:in std_logic;
		low:in std_logic;
		play0,play1,play2,play3:in integer range 0 to 9;
		decimal:in std_logic_vector(2 downto 0);
		overlatch:out std_logic;
		lowlatch:out std_logic;
		p0latch,p1latch,p2latch,p3latch:out integer range 0 to 9;
		delatch:out std_logic_vector(2 downto 0));
end component;
component display is
	port(
		cp1:in std_logic;
		low:in std_logic;
		overflow:in std_logic;
		p0,p1,p2,p3:in integer range 0 to 9;
		show_1:out std_logic_vector(6 downto 0);
		show_2:out std_logic_vector(6 downto 0);
		show_3:out std_logic_vector(6 downto 0);
		show_4:out std_logic_vector(6 downto 0);
		sel:out std_logic_vector(3 downto 0));
end component;
begin
	u1:dividefre4 port map(cp_20m,cp_1,cp_2,cp_3);
	u2:debounce port map(reset,cp_2,reset_1);
	u3:fretest port map(enable,cp_3,input,reset_1,overflow_1,low_1,
						play0_1,play1_1,play2_1,play3_1,decimal_1);
	u4:frelatch port map(reset_1,cp_3,overflow_1,low_1,play0_1,play1_1,
						play2_1,play3_1,decimal_1,overlatch_1,lowlatch_1,
						p0latch_1,p1latch_1,p2latch_1,p3latch_1,decimal);
	u5:display port map(cp_1,lowlatch_1,overlatch_1,p0latch_1,p1latch_1,
						p2latch_1,p3latch_1,show_1,show_2,show_3,show_4,sel);
end content;