debounce.vhd

来自「四位十进制数码显示、量程自动转换的数字频率计。」· VHDL 代码 · 共 22 行

--下层模块，防抖电路
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity debounce is
	port(
		key,cp:in std_logic;
		imp:out std_logic);
end debounce;
architecture base of debounce is
SIGNAL q1,q2:std_logic;
begin
	process(cp)
		begin
			if cp'event and cp='1' then
				q2<=q1;
				q1<=key;
			end if;
		end process;
		imp<=q1 and not q2;
	end base;