frelatch.vhd

四位十进制数码显示、量程自动转换的数字频率计。

--锁存器模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity frelatch is
	port(
		reset:in std_logic;
		cp3:in std_logic;
		overflow:in std_logic;
		low:in std_logic;
		play0,play1,play2,play3:in integer range 0 to 9;
		decimal:in std_logic_vector(2 downto 0);
		overlatch:out std_logic;
		lowlatch:out std_logic;
		p0latch,p1latch,p2latch,p3latch:out integer range 0 to 9;
		delatch:out std_logic_vector(2 downto 0));
	end frelatch;
architecture behavior of frelatch is
	begin
		process(cp3,reset,decimal)
		begin
			if reset='1' then--reset为'1'时置零
				overlatch<='0';
				lowlatch<='0';
				p0latch<=0;
				p1latch<=0;
				p2latch<=0;
				p3latch<=0;
				delatch<=decimal;
			elsif cp3 'event and cp3='0'then
		--当闸门处于下降沿时，将此计数计模块的各项输出值锁存
				overlatch<=overflow;
				lowlatch<=low;
				p0latch<=play0;
				p1latch<=play1;
				p2latch<=play2;
				p3latch<=play3;
				delatch<=decimal;
			end if;
		end process;
end behavior;