cmbwordtrig.vhd

用于逻辑分析仪的组合字触发程序,带四级触发字和一个屏蔽字,当满足触发条件是输出高电平,复位后清零

library ieee;
use ieee.std_logic_1164.all;

entity cmbwordtrig is
	port(	data : in std_logic_vector(31 downto 0);
		   tword : in std_logic_vector(31 downto 0);
		     sel : in std_logic_vector(2 downto 0);
			wr_n : in std_logic;
			 clk : in std_logic;
		   reset : in std_logic;
		    trig : out std_logic
		);
end entity;


architecture arch_cmbwordtrig of cmbwordtrig is
	type buffstc is array(0 to 3) of std_logic_vector(31 downto 0);
	signal buff : buffstc;
	signal bitbuff : std_logic_vector(0 to 3);
	signal pword : std_logic_vector(31 downto 0) := 
				"00000000000000000000000000000000";
	component wordtrig
		port(
				data,tword,pbword : in std_logic_vector(31 downto 0);
				        clk,reset : in std_logic;
				             trig : out std_logic
			);
	end component;
	
begin
	U0 : wordtrig port map(data,buff(0),pword,clk,reset,bitbuff(0));
	U1 : wordtrig port map(data,buff(1),pword,clk,reset,bitbuff(1));
	U2 : wordtrig port map(data,buff(2),pword,clk,reset,bitbuff(2));
	U3 : wordtrig port map(data,buff(3),pword,clk,reset,bitbuff(3));
	trig <= bitbuff(0) and 
			(bitbuff(1) or not (sel(0) or sel(1))) and 
			(bitbuff(2) or not sel(1)) and 
			(bitbuff(3) or not (sel(0) and sel(1)));
		

	process(wr_n)
	begin
		if(wr_n 'event and wr_n = '1' and reset = '1') then
			case sel is
				when "000" => buff(0) <= tword;
				when "001" => buff(1) <= tword;
				when "010" => buff(2) <= tword;
				when "011" => buff(3) <= tword;
				when others => pword <= tword;
			end case;
		end if;
	end process;
end architecture;

------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity wordtrig is
	port(	data : in std_logic_vector(31 downto 0);
		   tword : in std_logic_vector(31 downto 0);
		  pbword : in std_logic_vector(31 downto 0);
			 clk : in std_logic;
		   reset : in std_logic;
		    trig : out std_logic
		);
end entity;

architecture arch_wordtrig of wordtrig is 
begin
	process(clk,reset)
	begin
	if(clk 'event and clk = '1') then
		if ((data xnor tword) or pbword) = 
					"11111111111111111111111111111111" then
		trig <= '1';
		end if;
		if(reset = '1') then
		trig <= '0';
		end if;
	end if;
	end process;
end architecture;