bahe.vhd

设计四 拔河游戏机 1、 设计一个能进行拔河游戏的电路。 2、 电路使用15个(或9个)发光二极管

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bahe is
port(clk_4m,man_left,man_right,clr1,judger: in std_logic;
judger_out:out std_logic;
sel:out std_logic_vector(1 downto 0);
seg:out std_logic_vector(6 downto 0);
lamp:out std_logic_vector(12 downto 0)
);
end bahe;

architecture bahe_a of bahe is 

component Debunce 
PORT(
CP : IN STD_LOGIC; -- CLOCK 4MHZ
Key : IN STD_LOGIC; -- Input Signal
DOUT : OUT STD_LOGIC -- Debounce O/P

);
END component;

component counter 
PORT(
count : IN STD_LOGIC;
BIN : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
clr : IN STD_LOGIC
);
END component;


Signal s : STD_LOGIC;
signal left,right,na,nb,clk,clr,counta,countb:std_logic;
signal qp,left_num,right_num,num:std_logic_vector(3 downto 0);
signal lamper:std_logic_vector(14 downto 0);
signal b,judgerr,judger1:std_logic;
signal allen:std_logic_vector(4 downto 0);

begin 
u1:debunce port map(clk_4m,man_left,left);
u2:debunce port map(clk_4m,man_right,right);
u3:debunce port map(clk_4m,judger,judger1);
u5:counter port map(counta,left_num,clr);
u6:counter port map(countb,right_num,clr);

judger_out<=judgerr;
clr<=not clr1;
lamp<=lamper(13 downto 1);

process(clk_4m)
begin
if clk_4m'event and clk_4m='1' then
if judger1='1' then
judgerr<=not judgerr; 
end if; 
end if;
end process;


cou :block
signal q :std_logic_vector(22 downto 0);
begin 
process(clk_4M)
begin
if clk_4M'event and clk_4m='1' then
q<=q+1;
end if ;
end process;
clk<=q(20);
end block cou;

process(qp)
begin

if qp="0010" or qp="0000" then 
b<='1';
else b<='0';
end if;
end process;

counta<='1' when qp="0010" else
'0';
countb<='1' when qp="0000" else
'0';

process(clk_4m)
begin
if clr='1' or judgerr='0' or b='1' then qp<="1001";
elsif clk_4m'event and clk_4m='1' then 
if left='1' then qp<=qp+1;
elsif right='1' then qp<=qp-1;
end if;
end if;
end process;


panduan :block
begin 
p1:process(qp)
begin 
case qp is
when "1001" => lamper<="000000010000000";
when "1000" => lamper<="000000001000000";
when "0111" => lamper<="000000000100000";
when "0110" => lamper<="000000000010000";
when "0101" => lamper<="000000000001000";
when "0100" => lamper<="000000000000100";
when "0011" => lamper<="000000000000010";
when "0010" => lamper<="000000000000001";
when "1010" => lamper<="000000100000000";
when "1011" => lamper<="000001000000000";
when "1100" => lamper<="000010000000000";
when "1101" => lamper<="000100000000000";
when "1110" => lamper<="001000000000000";
when "1111" => lamper<="010000000000000";
when "0000" => lamper<="100000000000000";
when others =>NULL;
end case;
end process p1;
end block panduan;


---------轮显模块与计数器


Free_Counter : Block --计数器 & 产生扫描信号 
Signal Q : STD_LOGIC_VECTOR(24 DOWNTO 0);
Signal DLY,SDLY : STD_LOGIC;
Begin

PROCESS (clk_4m) -- 计数器计数 
Begin
IF clk_4m'Event AND clk_4m='1' then
DLY <= Q(21);
SDLY <= Q(14);
Q <= Q+1; --计数
END IF;
END PROCESS;

S <= Q(14); --about 250 Hz


process(s,right_num,left_num)
begin --扫描信号 
--SEL <= "01" WHEN S='0' ELSE
-- "10" WHEN S='1' ELSE
-- "01" when s=2 else
-- "10" when s=3 else
--"00"

--num <= left_num WHEN S='0' ELSE 
-- right_num WHEN S='1' ELSE
--left_num when s=2 else
--right_num when s=3 else
--"000000";
case s is 
when '1'=>sel<="10";num<=right_num;
when '0'=>sel<="01";num<=left_num;
when others=>sel<="00";num<=num;
end case;
end process; 
End Block Free_Counter; 


SEVEN_SEGMENT : Block -- Binary Code -> Segment 7 Code
Begin
--gfedcba
SEG <= "0111111" WHEN NUM = 0 ELSE
"0000110" WHEN NUM = 1 ELSE
"1011011" WHEN NUM = 2 ELSE
"1001111" WHEN NUM = 3 ELSE
"1100110" WHEN NUM = 4 ELSE
"1101101" WHEN NUM = 5 ELSE
"1111101" WHEN NUM = 6 ELSE
"0000111" WHEN NUM = 7 ELSE
"1111111" WHEN NUM = 8 ELSE
"1101111" WHEN NUM = 9 ELSE
"1110111" WHEN NUM = 10 ELSE
"1111100" WHEN NUM = 11 ELSE
"0111001" WHEN NUM = 12 ELSE
"1011110" WHEN NUM = 13 ELSE
"1111001" WHEN NUM = 14 ELSE
"1110001" WHEN NUM = 15 ELSE
"0000000";
End Block SEVEN_SEGMENT; 


end bahe_a;