代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/168685/9902060
vhd decode.vhd
--
-- decode.vhd
--
-- cpu decode of JOP3
--
-- generate control for pc and stack
--
--
-- resources on ACEX1K30-3
--
-- xxx LCs, 42.0 MHz
--
-- todo:
--
--
-- 2001-07-03 extracted
www.eeworm.com/read/168683/9902069
vhd bcfetch.vhd
--
-- bcfetch.vhd
--
-- Java bc fetch and address translation for JVM
--
-- resources on ACEX1K30-3
--
-- bytecode LCs, max ca. xx MHz
--
-- todo:
--
-- 2001-11-16 split from fetch.vhd, re
www.eeworm.com/read/364522/9904386
vhd scan.vhd
--（2）显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan is
port(clk:in std_logic; ---20MHz时钟输入
a:in std_logic_vector(31 d
www.eeworm.com/read/168350/9919407
vhd time.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity time is
port(clkin:in std_logic;
sp:in std_logic;
set:in std_logic;
re
www.eeworm.com/read/364157/9920049
vhd compressor_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : JPEG Hardware Compressor Testbench
-- Design : jpeg
-- Author : Victor
www.eeworm.com/read/364037/9923731
vhd shuma_2dt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2dt is
port(reset,en,data: in std_logic;
clk: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:
www.eeworm.com/read/364037/9923755
vhd shuma_2jt.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2jt is
port(data: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:out std_logic_vector(5 downto
www.eeworm.com/read/364037/9923861
vhd maichong.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity maichong is
port(reset,en,data: in std_logic;
out0:out std_logic_vector(7 downto 0)
);
end maichong;
architec
www.eeworm.com/read/364037/9923913
vhd shuma_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuma_2 is
port(data: in std_logic;
out0:out std_logic_vector(7 downto 0);
out1:out std_logic_vector(5 downto 0
www.eeworm.com/read/363985/9926893
vhd pe_pkg.vhd
------------------------------------------------------------------------
--
-- Copyright (C) 1998-1999, Annapolis Micro Systems, Inc.
-- All Rights Reserved.
--
--------------------------------