代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/174989/9565793
bak dregister.vhd.bak
library IEEE;
use IEEE.std_logic_1164.all;
entity DRegister is
port( op: in std_logic;
clk: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downt
www.eeworm.com/read/174812/9573415
m uwb_sv_params.m
function [Lam,lambda,Gam,gamma,std_ln_1,std_ln_2,nlos,std_shdw] = uwb_sv_params( cm_num )
% Return S-V model parameters for standard UWB channel models
% Lam Cluster arrival rate (clusters per ns
www.eeworm.com/read/370892/9577597
vhd autoseller.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity autoseller is
port(clk :in std_logic;
colin :in std_logic_vector(3
www.eeworm.com/read/370892/9577601
vhd suocun.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity suocun is
port ( clk2 :in std_logic;
www.eeworm.com/read/170457/9806354
vhd components_pack.vhd
library ieee;
use ieee.std_logic_1164.all;
package components_pack is
-- D-flipflop
component dff
generic (
w : integer);
port (
clk, rst : in std_logic;
www.eeworm.com/read/170347/9809208
vhd andarith.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS -- 选通与门模块
PORT ( ABIN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOU
www.eeworm.com/read/170347/9809221
vhd multi8x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY MULTI8X8 IS -- 8位乘法器顶层设计
PORT ( CLKK,START : IN STD_LOGIC;
A,
www.eeworm.com/read/170345/9809227
vhd songer.vhd
LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK12MHZ : IN STD_LOGIC; --音调频率信号
CLK8H
www.eeworm.com/read/366548/9809382
vhd miso.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity miso is
port(
clk : in std_logic;
miso: in std_logic;
sck : out std_logic;
cs : out std_logic;
dout:
www.eeworm.com/read/170195/9814846
vhd hour.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hour is
Port ( clk : in std_logic;
reset : in std_logic;