miso.vhd

SPI接口的vhdl代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity miso is
port(
	clk : in std_logic;
	miso: in std_logic;
	sck : out std_logic;
	cs  : out std_logic;
	dout: out std_logic_vector(11 downto 0)
	);
end miso;

architecture behav of miso is
signal inter_bus_out:std_logic_vector(7 downto 0);
signal spcr:std_logic_vector(7 downto 0);
signal spdr:std_logic_vector(11 downto 0);
signal d_reg:std_logic_vector(11 downto 0);
signal count:std_logic_vector(5 downto 0);
signal cnt_read:std_logic_vector(7 downto 0);
signal sck,count_en,start,read,cnt_en:std_logic;
begin
	--mpu read process
	dout <= d_reg;	
	--read delay
	process(clk,cnt_read)
	begin
		if rising_edge(clk) then
			cnt_read <= cnt_read+1;
			if cnt_read = "00010100" then
				start <= '1';
			elsif cnt_read="00010110" then
				start <= '0';
			elsif cnt_read="00111100" then
				cs <= '1';
			elsif cnt_read="00000000" then
				d_reg <= spdr;
				cs <= '0';
			end if;
		end if;
	end process;
	
			
	--mspi process
	process(start,sck)
	begin
		--if(start='1')then
			--spdr<="000000000000";
		if falling_edge(sck) then				
			if(count<"011011" and count/="000001")then
				--mosi<=spdr(11);
				spdr <= spdr(10 downto 0) & miso;
			end if;
		end if;
	end process;
	
	process(clk,start,count)
	begin
		if rising_edge(clk) then
			if count="100001" then
				count_en <= '0';
			elsif start='1' then
				count_en <= '1';
			end if;
		end if;
	end process;
	
	process(clk,count_en)
	begin
		if rising_edge(clk) then
			if count_en='1' then
				count <= count + 1;
			else 
				count <= "000000";
			end if;
		end if;
	end process;

	sck <= count(0);
	sck <= sck;
end behav;