spi_interface.vhd

来自「SPI接口的vhdl代码」· VHDL 代码 · 共 54 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity spi_interface is
port(
     clk : in std_logic;
     cs  : in std_logic;
     sclk: in std_logic;
     din : in std_logic_vector(7 downto 0);
     mosi: out std_logic
    );
end spi_interface;

architecture behave of spi_interface is
type send_states is(cs_starting,waiting,sending,shifting,increment,cs_over);
signal send_state : send_states;
signal q:std_logic;
begin
 process(clk,cs,send_state)
  begin
    if cs='1' then 
       mosi<='0';
       q<=din;
    elsif rising_edge(clk) then
      case send_state is
        when cs_starting=>
               if sclk='1' then
                  send_state<=waiting;
               end if;
        when waiting=>
                send_state<=sending;
        when sending=>
                if i>7 then
                  mosi<=q(0);
                else
                  mosi<='0';
                end if;
                 send_state<=shifting;
        when shiting=>
                if i>7 then
                   q<=('0' & q(7 downto 1));      --right shifting
                end if;
                send_state<=increment;
        when increment=>
                i:=i+1;
                send_state<=cs_over;
        when cs_over=>
                
                
       end case;
    end if;
end process;