multi8x8.vhd

移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY MULTI8X8 IS                            -- 8位乘法器顶层设计
    PORT ( CLKK,START  : IN STD_LOGIC;
                 A,  B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                  DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END MULTI8X8;
ARCHITECTURE struc OF MULTI8X8 IS
COMPONENT ARICTL
    PORT (  CLK, START : IN STD_LOGIC;
         CLKOUT, RSTALL : OUT STD_LOGIC  );
END COMPONENT;
COMPONENT ANDARITH
    PORT (  ABIN : IN STD_LOGIC;
              DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  );
END COMPONENT;
COMPONENT ADDER8B
    PORT (CIN : IN STD_LOGIC;
             A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          COUT : OUT STD_LOGIC );
END COMPONENT;
COMPONENT SREG8B
    PORT (  CLK, LOAD : IN STD_LOGIC;
             DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
              QB : OUT STD_LOGIC  );
END COMPONENT;
COMPONENT REG16B
    PORT (   CLK, CLR : IN STD_LOGIC;
        D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
        Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)  );
END COMPONENT;
    SIGNAL GNDINT, INTCLK, RSTALL, NEWSTART, QB : STD_LOGIC;
    SIGNAL ANDSD : STD_LOGIC_VECTOR(7 DOWNTO 0);
     SIGNAL DTBIN : STD_LOGIC_VECTOR(8 DOWNTO 0);
    SIGNAL DTBOUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
    DOUT <= DTBOUT;   GNDINT <= '0';
PROCESS(CLKK,START)
BEGIN
	IF START='1' THEN NEWSTART<='1';
	ELSIF CLKK='0' THEN	NEWSTART<='0';	END IF;
END PROCESS;
U1 : ARICTL  PORT MAP(CLK=>CLKK,START=>NEWSTART, CLKOUT=>INTCLK, RSTALL=>RSTALL);
U2 : SREG8B  PORT MAP(CLK=>INTCLK, LOAD=>RSTALL, DIN=>B, QB=>QB  );
U3 : ANDARITH PORT MAP(ABIN => QB, DIN => A,DOUT => ANDSD);
U4 : ADDER8B  PORT MAP(CIN => GNDINT, A=>DTBOUT(15 DOWNTO 8), B=>ANDSD,    
                S => DTBIN(7 DOWNTO 0), COUT => DTBIN(8) );
U5 : REG16B   PORT MAP(CLK=>INTCLK, CLR=>RSTALL, D=>DTBIN, Q=>DTBOUT );
   END struc;