hour.vhd

来自「24,60,100进制的计数器」· VHDL 代码 · 共 37 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hour is
    Port ( clk : in std_logic;
         reset : in std_logic;
            co : out std_logic;
            miaol : buffer std_logic_vector(3 downto 0);
            miaoh : buffer std_logic_vector(3 downto 0);
            fenl : buffer std_logic_vector(3 downto 0);
            fenh : buffer std_logic_vector(3 downto 0);
            shil : buffer std_logic_vector(3 downto 0);
            shih : buffer std_logic_vector(2 downto 0) );
end hour;
architecture shizhong of hour is
component counter60
Port ( clk : in std_logic;
           reset : in std_logic;
          co : out std_logic;
          dl : buffer std_logic_vector(3 downto 0);
          dh : buffer std_logic_vector(3 downto 0));
end component;
component counter24
 Port ( clk : in std_logic;
           reset : in std_logic;
          co : out std_logic;
          dl : buffer std_logic_vector(3 downto 0);
          dh : buffer std_logic_vector(2 downto 0));
end component;
signal s1,s2: std_logic;
begin
u1:counter60 port map(clk,reset,s1,miaol,miaoh);
u2:counter60 port map(s1,reset,s2,fenl,fenh);
u3:counter24 port map(s2,reset,co,shil,shih);
end shizhong;