components_pack.vhd

使用vhdl编写的一段程序。 主要功能是声音周期计算

  library ieee;
  use ieee.std_logic_1164.all;

  package components_pack is

    -- D-flipflop
    component dff
      generic (
        w : integer);
      port (
        clk, rst : in  std_logic;
        d        : in  std_logic_vector(w-1 downto 0);
        q        : out std_logic_vector(w-1 downto 0));
    end component;
    
  
    -- Addition unit
    component adder
      generic (
        w1 : integer;
        w2 : integer);
      port (
        in1    : in  std_logic_vector(w1-1 downto 0);
        in2    : in  std_logic_vector(w2-1 downto 0);
        output : out std_logic_vector(w1 downto 0));
    end component;
 
    
    -- Fixed multiplication unit
    component fixed_mult
      generic (
        w            : integer;
        w_m          : integer;
        multiplicand : integer);
      port (
        input  : in  std_logic_vector(w-1 downto 0);
        output : out std_logic_vector(w+w_m-1 downto 0));
    end component;
    

end package;
-------------------------------------------------------------------------------
-- component dff
-------------------------------------------------------------------------------

  library ieee;
  use ieee.std_logic_1164.all;

  entity dff is
    generic (
      w : integer);
    port (
      clk, rst : in  std_logic;
      d        : in  std_logic_vector(w-1 downto 0);
      q        : out std_logic_vector(w-1 downto 0));
  end dff;

  architecture behavioral of dff is

  begin  -- behavioral

    flipflop : process (clk, rst)
    begin  -- process flipflop
      if clk'event and clk='1' then
       if rst = '0' then               -- synchronous reset (active low)
          q <= (others => '0');
       else
          q <= d;
       end if;
      end if;
    end process flipflop;

  end behavioral;
-------------------------------------------------------------------------------
-- component adder
-------------------------------------------------------------------------------

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_signed.all;
  use ieee.std_logic_arith.all;

  entity adder is
    generic (
      w1 : integer;
      w2 : integer);
    port (
      in1    : in  std_logic_vector(w1-1 downto 0);
      in2    : in  std_logic_vector(w2-1 downto 0);
      output : out std_logic_vector(w1 downto 0));
  end adder;

  architecture behavioral of adder is

  begin  -- behavioral

    add : process (in1, in2)
    begin  -- process add
      output <= sxt(in1, w1+1) + in2;
    end process add;

  end behavioral;

-------------------------------------------------------------------------------
-- component fixed_mult
-------------------------------------------------------------------------------

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_signed.all;
  use ieee.std_logic_arith.all;

  entity fixed_mult is
    generic (
      w            : integer;
      w_m          : integer;
      multiplicand : integer);
    port (
      input  : in  std_logic_vector(w-1 downto 0);
      output : out std_logic_vector(w+w_m-1 downto 0));
  end fixed_mult;

  architecture behavioral of fixed_mult is

  begin  -- behavioral

    process (input)
    begin  -- process
      output <= input * conv_std_logic_vector(multiplicand, w_m);
    end process;


  end behavioral;