autoseller.vhd

（1）、自动售货机可以出售4种货物

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity autoseller is
   port(clk   :in std_logic;
        colin :in std_logic_vector(3 downto 0);
        sel   :out std_logic_vector(2 downto 0);
        seg   :out std_logic_vector(6 downto 0);
        row   :out std_logic_vector(3 downto 0);
        light :out std_logic;
        dot   :out std_logic);
 end;

architecture a of autoseller is
   signal line                   :std_logic_vector(3 downto 0);
   signal bcdminl,bcdmol,coll    :std_logic_vector(3 downto 0);
   signal cp1,cp2,cp3,numlet,l,dp:std_logic;
   component fenpin is
       port(clk           :in std_logic;
            clk1,clk2,clk3:out std_logic);
   end component;

component antivib is
port(clk2,key:in std_logic;
     keyout  :out std_logic);
end component;
component keyin is
port(clk1      :in std_logic;
     col       :in std_logic_vector(3 downto 0);
     row,bcdmin:out std_logic_vector(3 downto 0));
end component;

component suocun is
port(clk2      :in std_logic;
     bcdmin,col:in std_logic_vector(3 downto 0);
     bcdmo     :out std_logic_vector(3 downto 0));
end component;
component disp is
port(clk3      :in std_logic;
     bcdmo     :in std_logic_vector(3 downto 0);
     sel   :out std_logic_vector(2 downto 0);
     seg   :out std_logic_vector(6 downto 0);
     light :out std_logic;
     dot   :out std_logic);
 end component;
begin 
    u1:fenpin port map(clk,cp1,cp2,cp3);
    U2:antivib port map(cp2,colin(3),coll(3));
    u3:antivib port map(cp2,colin(2),coll(2));
    u4:antivib port map(cp2,colin(1),coll(1));
    u5:antivib port map(cp2,colin(0),coll(0));
    u6:keyin port map(cp1,coll,row,bcdminl);
    u7:suocun port map(cp2,bcdminl,coll,bcdmol);
    U8:disp  port map (cp3,bcdmol,sel,seg,light,dot);
end a;