代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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vhd top.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TOP IS PORT(CLK : IN STD_LOGIC; STATUS : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED : OUT STD_LOGIC_VE
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vhd dfre.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DFRE IS PORT(iclk : IN STD_LOGIC; iRES : IN STD_LOGIC; oNUM: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); E
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www.eeworm.com/read/385516/8801982

bak key.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY KEY IS PORT( iRES: IN STD_LOGIC; iKEY: IN STD_LOGIC_VECTOR(4 DOWNTO 0); oKEY: OUT STD_LOGIC_VECTOR(4
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www.eeworm.com/read/385516/8802017

vhd counter.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER IS PORT(iclk : IN STD_LOGIC; iNUM: IN STD_LOGIC_VECTOR(2 DOWNTO 0); oIS : OUT STD_LOGIC_VECT
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www.eeworm.com/read/385516/8802042

bak counter.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER IS PORT(iclk : IN STD_LOGIC; iNUM: IN STD_LOGIC_VECTOR(2 DOWNTO 0); oIS : OUT STD_LOGIC_VECT
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vhd key.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY KEY IS PORT( iRES: IN STD_LOGIC; iKEY: IN STD_LOGIC_VECTOR(4 DOWNTO 0); oKEY: OUT STD_LOGIC_VECTOR(4
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www.eeworm.com/read/385516/8802316

bak dfre.vhd.bak

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DFRE IS PORT(iclk : IN STD_LOGIC; iRES : IN STD_LOGIC; oNUM: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); E
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www.eeworm.com/read/429564/8802664

vhd poc.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY POC IS PORT(A0,RW,CLOCK,CS,RDY,RESET:IN STD_LOGIC; DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0); TR,IRQ:OUT STD_LOGIC;
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www.eeworm.com/read/429564/8802668

vhd printer.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY PRINTER IS PORT(CLOCK,TR,RESET:IN STD_LOGIC; PD:IN STD_LOGIC_VECTOR(7 DOWNTO 0); RDY:BUFFER STD_LOGIC;
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www.eeworm.com/read/385315/8809610

txt 7bjq.txt

要求用VHDL语言设计7人表决器电路，了解变量和信号的区别，了解进程内部顺序语句及外部并行语句的区别。library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY vote7 IS PORT ( men: IN std_logic_vector(6 do
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