📄 top.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TOP IS
PORT(CLK : IN STD_LOGIC;
STATUS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END TOP;
ARCHITECTURE run OF TOP IS
COMPONENT AUTOLED IS
PORT(CLK : IN STD_LOGIC;
STATUS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT;
COMPONENT DFRE IS
PORT(iclk : IN STD_LOGIC;
oclk : OUT STD_LOGIC);
END COMPONENT;
SIGNAL DCLK : STD_LOGIC;
BEGIN
U1 : DFRE PORT MAP(iclk => CLK, oclk => DCLK);
U2 : AUTOLED PORT MAP(CLK => DCLK, STATUS => STATUS, LED => LED);
END run;
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