📄 dfre.vhd
字号:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DFRE IS
PORT(iclk : IN STD_LOGIC;
iRES : IN STD_LOGIC;
oNUM: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END DFRE;
ARCHITECTURE run OF DFRE IS
BEGIN
PROCESS (iRES, iclk)
VARIABLE fre: STD_LOGIC_VECTOR(25 DOWNTO 0);
VARIABLE V_oNUM : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
BEGIN
IF iclk'EVENT AND iclk = '1'
THEN IF iRES = '0'
THEN fre := "00000000000000000000000000";
V_oNUM := "000";
ELSIF fre = "01011111010111100001000000"
THEN fre := "00000000000000000000000000";
IF V_oNUM = "101"
THEN V_oNUM := "001";
ELSE V_oNUM := V_oNUM + '1';
END IF;
ELSE fre := fre + '1';
END IF;
END IF;
oNUM <= V_oNUM;
END PROCESS;
END run;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -