代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/433021/8551950

vhd 可控脉冲发生器.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity pluse is port (data : in std_logic_vector(7 downto 0); start,clk : in std
www.eeworm.com/read/433021/8552033

vhd 带load_clr等功能的寄存器.vhd

--8-bit Register with Synchronous Load and Clear The design entity shows the standard way of describing a register using a synchronous process, ie. a process containing a single wait statement which i
www.eeworm.com/read/433021/8552113

xml coregen.xml

www.eeworm.com/read/389007/8555664

vhd caideng.vhd

library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity caideng is port(clk ,clr:in std_logic; dout:out std_logic_vector(7 downto 0)); end; architecture bhv of c
www.eeworm.com/read/188211/8560450

vhd cnt20.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity cnt20 is port (stop,start,reset,clk:in std_logic; q:out std_logic_vector(7 downto 0);
www.eeworm.com/read/188209/8560739

vhd control.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity control is port ( clk1024,clk500,sa,sb,sc,en: in std_logic; q1 : in std_logic_vector(7 downto 0); q2
www.eeworm.com/read/188207/8561030

vhd speed.vhd

--16 mtimes; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY speed IS PORT( clk,reset,start : IN STD_LOGIC; k : IN STD_LOGIC_VECTOR(4 downto 0); clk
www.eeworm.com/read/432767/8575828

vhd bcdto7seg.vhd

library ieee; use ieee.std_logic_1164.all; entity converter is port( db:in std_logic_vector(3 downto 0); seg:out std_logic_vector(6 downto 0) ); end converter; architecture a of con
www.eeworm.com/read/288162/8650751

vhd write_reg.vhd

library ieee; use ieee.std_logic_1164.all; entity write_reg is port( ale : in std_logic; ad_in : in std_logic_vector(7 downto 0); sa_h : in std_logic_vector(15 downto 8);
www.eeworm.com/read/431824/8651711

vhd csa_2weight.vhd

-- hds header_start -- -- VHDL Architecture FPdivider24.csa_2weight.untitled -- -- Created: -- by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P) -- at - 16:08:52 2003/11/26 -- -- Generat