cnt20.vhd

4人抢答器的硬件描述语言设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cnt20 is
port
         (stop,start,reset,clk:in std_logic;
          q:out std_logic_vector(7 downto 0);
          yellow,green,red:out std_logic);
end;

architecture behavioral of cnt20 is
signal cao_v:std_logic_vector(1 downto 0);
BEGIN
PROCESS (reset,STOP,RESET,CLK)
  VARIABLE TMP1:integer;
  VARIABLE tmp2:integer;
  VARIABLE CA:integer;
BEGIN
	IF reset='1' THEN
	  TMP1:=0;tmp2:=2;CA:=0;
	ELSIF(clk'event and clk='1')THEN
	   if(stop='0')then
        if(start='1')then
          if(tmp1=0)then
            if(tmp2=0)then
              ca:=1;
            else
              tmp2:=tmp2-1;
              tmp1:=9;
            end if;
          else
           tmp1:=tmp1-1;
          end if;
        end if;
       end if;    
  	END IF;
    cao_v<=conv_std_logic_vector(ca,1);
    yellow<=cao_v(0);
    q(7 downto 4)<=conv_std_logic_vector(tmp2,4);
    q(3 downto 0)<=conv_std_logic_vector(tmp1,4);       		
	END PROCESS;
green<=stop and start;
red<=stop and ( not start);
end behavioral;