csa_2weight.vhd

是Nios II處理器下客製化指令的一個32位元浮點數除法器

-- hds header_start
--
-- VHDL Architecture FPdivider24.csa_2weight.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:08:52 2003/11/26
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


entity csa_2weight is
port(
     a:in std_logic_vector(1 downto 0);
     b:in std_logic_vector(1 downto 0);
     c:in std_logic_vector(1 downto 0);
     d:in std_logic_vector(1 downto 0);
     e:in std_logic_vector(1 downto 0);
     f:in std_logic_vector(1 downto 0);
     g:in std_logic_vector(1 downto 0);
     h:in std_logic_vector(1 downto 0);
     
    cin_0:in std_logic;
    cin_1:in std_logic;
    cin_2:in std_logic;
    cin_3:in std_logic;  
    cin_4:in std_logic;
    cin_5:in std_logic;   

    cout_0:out std_logic;
    cout_1:out std_logic;
    cout_2:out std_logic;
    cout_3:out std_logic;
    cout_4:out std_logic;
    cout_5:out std_logic;

    cout_to_cpa:out std_logic_vector(1 downto 0);
     sum_to_cpa:out std_logic_vector(1 downto 0));

end csa_2weight;

architecture arch of csa_2weight is

component csa_1bit
    port(
         a:in std_logic;
         b:in std_logic;
         c:in std_logic;
       sum:out std_logic;
      carry:out std_logic);
end component;
 
signal zero:std_logic:='0';
signal u00_s:std_logic;
signal u00_c:std_logic;
signal u01_s:std_logic;
signal u01_c:std_logic;
signal u02_s:std_logic;
signal u02_c:std_logic;
signal u03_s:std_logic;
signal u04_s:std_logic;
signal u05_s:std_logic;

signal u10_s:std_logic;
signal u10_c:std_logic;
signal u11_s:std_logic;
signal u11_c:std_logic;
signal u12_s:std_logic;
signal u13_s:std_logic;

signal u20_s:std_logic;
signal u20_c:std_logic;
signal u21_s:std_logic;



begin

--row 0  begin----------------------
u00:csa_1bit port map(
        a=>a(0),
         b=>b(0),
         c=>c(0),
       sum=>u00_s,
      carry=>u00_c);

u01:csa_1bit port map(
        a=>d(0),
         b=>e(0),
         c=>f(0),
       sum=>u01_s,
      carry=>u01_c);

u02:csa_1bit port map(
        a=>g(0),
         b=>h(0),
         c=>zero,
       sum=>u02_s,
      carry=>u02_c);

u03:csa_1bit port map(
        a=>a(1),
         b=>b(1),
         c=>c(1),
       sum=>u03_s,
      carry=>cout_0);

u04:csa_1bit port map(
        a=>d(1),
         b=>e(1),
         c=>f(1),
       sum=>u04_s,
      carry=>cout_1);

u05:csa_1bit port map(
        a=>g(1),
         b=>h(1),
         c=>zero,
       sum=>u05_s,
      carry=>cout_2);


--row 1 begin------------------------
u10:csa_1bit port map(
        a=>cin_0,
         b=>cin_1,
         c=>u00_s,
       sum=>u10_s,
      carry=>u10_c);

u11:csa_1bit port map(
        a=>cin_2,
         b=>u01_s,
         c=>u02_s,
       sum=>u11_s,
      carry=>u11_c);

u12:csa_1bit port map(
        a=>u00_c,
         b=>u03_s,
         c=>u04_s,
       sum=>u12_s,
      carry=>cout_3);

u13:csa_1bit port map(
        a=>u01_c,
         b=>u02_c,
         c=>u05_s,
       sum=>u13_s,
      carry=>cout_4);



--row 2 begin-------------------------
u20:csa_1bit port map(
        a=>cin_3,
         b=>cin_4,
         c=>u10_s,
       sum=>u20_s,
      carry=>u20_c);


u21:csa_1bit port map(
        a=>u10_c,
         b=>u12_s,
         c=>u13_s,
       sum=>u21_s,
      carry=>cout_5);


--row 3 begin-----------------------
u30:csa_1bit port map(
        a=>cin_5,
         b=>u20_s,
         c=>u11_s,
       sum=>sum_to_cpa(0),
      carry=>cout_to_cpa(0));


u31:csa_1bit port map(
        a=>u20_c,
         b=>u11_c,
         c=>u21_s,
       sum=>sum_to_cpa(1),
      carry=>cout_to_cpa(1));
end arch;