rca_20bit.vhd

来自「是Nios II處理器下客製化指令的一個32位元浮點數除法器」· VHDL 代码 · 共 68 行

-- hds header_start
--
-- VHDL Architecture FPdivider24.rca_7bit.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:36:21 2003/11/26
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;





entity rca_20bit is 
--generic(length:integer:=7);
port(
     x:in std_logic_vector(19 downto 0);
     y:in std_logic_vector(19 downto 0);
     s:out std_logic_vector(19 downto 0));
end rca_20bit;

architecture arch of rca_20bit is

component FA_1bit
     port(
         a:in std_logic;
         b:in std_logic;
       cin:in std_logic;
         s:out std_logic;
      cout:out std_logic);
end component;

signal cp:std_logic_vector(19 downto 0);
signal zero:std_logic:='0';

begin
   CPA_gen:for i in 0 to 19 generate

    first:if i=0 generate
    FA_1bit_adder: FA_1bit port map(
                           a=>x(i),
											 b=>y(i),
                         cin=>zero,
                           s=>s(i),
                        cout=>cp(i));
          end generate;

    other:if (i>0) generate
    FA_1bit_adder: FA_1bit port map(
                           a=>x(i),
											 b=>y(i),
                         cin=>cp(i-1),
                           s=>s(i),
                        cout=>cp(i));
          end generate; 
   end generate;
end arch;