fa_1bit.vhd

来自「是Nios II處理器下客製化指令的一個32位元浮點數除法器」· VHDL 代码 · 共 35 行

-- hds header_start
--
-- VHDL Architecture FPdivider24.FA_1bit.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:38:02 2003/11/26
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;




entity fa_1bit is 
port(
     a:in std_logic;
     b:in std_logic;
   cin:in std_logic;
     s:out std_logic;
  cout:out std_logic);
end fa_1bit;

architecture a of fa_1bit is 
begin

s<=(a xor b) xor cin;
cout<=(a and b) or (cin and (a or b));

end a;