mult_ax.vhd

来自「是Nios II處理器下客製化指令的一個32位元浮點數除法器」· VHDL 代码 · 共 37 行

-- hds header_start
--
-- VHDL Architecture FPdivider24.mult_ax.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:15:52 2003/12/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mult_ax IS
   PORT( 
      in_a      : IN     std_logic_vector (23 DOWNTO 0);
      in_x      : IN     std_logic_vector (7 DOWNTO 0);
      result_ax : OUT    std_logic_vector (29 DOWNTO 0)
   );

-- Declarations

END mult_ax ;

-- hds interface_end
ARCHITECTURE untitled OF mult_ax IS
signal tmp:std_logic_vector(32 downto 0);
signal tmp_x:std_logic_vector(8 downto 0);
BEGIN
tmp_x<='0'&in_x;
tmp<=unsigned(in_a)*unsigned(tmp_x);
result_ax<=tmp(31 downto 2);
END untitled;