带load_clr等功能的寄存器.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 21 行

--8-bit Register with Synchronous Load and Clear
The design entity shows the standard way of describing a register using a synchronous process, ie. a process containing a single wait statement which is triggered by a rising edge on the clock input.
library ieee;
use ieee.std_logic_1164.all;
entity reg8 is
port(clock, clear, load : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0));
end entity reg8;
architecture v1 of reg8 is
begin
reg_proc : process
begin
wait until rising_edge(clock);
if clear = '1' then
q <= (others => '0');
elsif load = '1' then
q <= d;
end if;
end process;
end architecture v1;