speed.vhd

硬件出租车记数器完整的VHDL语言设计

--16 mtimes;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY speed IS
	PORT(
		clk,reset,start		: IN	STD_LOGIC;
		k		: IN	STD_LOGIC_VECTOR(4 downto 0);
		clkout 	: OUT	STD_LOGIC);
END speed;
ARCHITECTURE a OF speed IS
	SIGNAL count1 : STD_LOGIC_VECTOR(1 downto 0);
	SIGNAL tempclk,clks	: STD_LOGIC;
	SIGNAL kinside	: STD_LOGIC_VECTOR(4 downto 0);

BEGIN
kinside<="00000"-k;

clks_label:
PROCESS (reset,clk)
variable count2 :	 STD_LOGIC_VECTOR(4 downto 0);

BEGIN
IF reset='1'  THEN
    count2:="00000";
ELSIF clk'event and clk='1' THEN
if start='1'then
    if count2=kinside  then count2:="00000";  end if;
	if not (k="00000") then count2:=count2+1; end if;
	if count2="00001" then tempclk<=not tempclk; end if;
END IF;
end if;
END PROCESS clks_label;
clkout<=tempclk;

END a;