代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/336141/12474952
vhd ctl_2.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_2 is
Port(
clk :in std_logic; -- 作时钟使用
P1_0 :in std_logic; -- 控制脉冲宽度
T :in std_logic_vector(19 downto 0); -- 20位中间控制信号
Q :
www.eeworm.com/read/335962/12488239
vhd display1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--调时和调价输出的切换
entity display1 is
port(
flag1 :in std_logic; --调价标志
flag2 :in std_logic;
www.eeworm.com/read/335962/12488362
vhd displayswitch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity displayswitch is
port
( switch : in std_logic;
up : in std_logic_vector(3 downto 0);
pri
www.eeworm.com/read/335962/12488495
vhd shezhi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shezhi is
port
( mode : in std_logic;
sure : in std_logic;
up : in std_logic
www.eeworm.com/read/335670/12509369
vhd multi8x8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity multi8x8 is port(
clk : in std_logic;
start : in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 dow
www.eeworm.com/read/147842/12516083
vhd etester.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ETESTER IS
PORT(BCLK,TCLK,CLR,CL,SPUL : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
START,EEND :
www.eeworm.com/read/335509/12519903
vhd contral.vhd
-- MAX+plus II VHDL Template
-- Clearable flipflop with enable
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY contrOl IS
PORT
(
clk : IN STD_LOGI
www.eeworm.com/read/147654/12541014
txt 新建 文本文档.txt
程序一：
1． 移位寄存器：
library ieee;
use ieee.std_logic_1164.all;
entity reg is
port(clk,reset:in std_logic;
data:in std_logic_vector(7 downto 0);--输入的数据
outdata:out std_logic_
www.eeworm.com/read/335284/12541629
vhd bel.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bel is
port(ms1,ss1:in std_logic_vector(7 downto 4);
ms2,ss2:in std_logic_
www.eeworm.com/read/335284/12541698
vhd show.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity show is
port(hs1,ms1,ss1:in std_logic_vector(7 downto 4);
hs2,ms2,ss2:in s