📄 show.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity show is
port(hs1,ms1,ss1:in std_logic_vector(7 downto 4);
hs2,ms2,ss2:in std_logic_vector(3 downto 0);
bh1,bm1,bs1:in std_logic_vector(7 downto 4);
bh2,bm2,bs2:in std_logic_vector(3 downto 0);
h0,h1,m0,m1,s0,s1: out std_logic_vector(3 downto 0);
reset,sel: in std_logic);
end show;
architecture showx of show is
begin
cm:process(reset,sel)
begin
if reset='1' then
h0<="0000";
h1<="0000";
m0<="0000";
m1<="0000";
s0<="0000";
s1<="0000";
elsif reset='0' then
if sel='1' then
h0<=hs1;
h1<=hs2;
m0<=ms1;
m1<=ms2;
s0<=ss1;
s1<=ss2;
elsif sel='0' then
h0<=bh1;
h1<=bh2;
m0<=bm1;
m1<=bm2;
s0<=bs1;
s1<=bs2;
end if;
end if;
end process cm;
end showx;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -