ctl_2.vhd

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Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_2 is
Port(
	clk		:in std_logic;						-- 作时钟使用
	P1_0	:in std_logic;						-- 控制脉冲宽度
	T		:in std_logic_vector(19 downto 0);	-- 20位中间控制信号
	Q		:out std_logic_vector(19 downto 0);	-- 开关控制信号
	NQ		:out std_logic_vector(19 downto 0)	-- 开关控制信号
	);
End ctl_2;
Architecture behavior of ctl_2 is
	signal tmp1,tmp2		:std_logic_vector(19 downto 0);			
Begin		
	Q<=tmp1; 
	NQ<=tmp2; 	
	process(clk,P1_0)
	begin
		if (P1_0='0') then					-- 关闭输出信号，形成脉冲
			tmp1<="00000000000000000000";
			tmp2<="00000000000000000000";
		elsif (clk'event and clk='0') then
			if (P1_0='1') then
				tmp1<=T;
				tmp2<=NOT T;
			end if;		
		end if;
	end process;
End behavior;